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The rate at which graphene is used in different fields of science and engineering has only increased over the past decade and shows no indication of saturating. At the same time, the most common source of high-quality graphene is through chemical vapor deposition (CVD) growth on copper foils with subsequent wet transfer steps that bring environmental problems and technical challenges due to the compliance of copper foils. To overcome these issues, thin copper films deposited on silicon wafers have been used, but the high temperatures required for graphene growth can cause dewetting of the copper film and consequent challenges in obtaining uniform growth. In this work, we explore sapphire as a substrate for the direct growth of graphene without any metal catalyst at conventional metal CVD temperatures. First, we found that annealing the substrate prior to growth was a crucial step to improve the quality of graphene that can be grown directly on such substrates. The graphene grown on annealed sapphire was uniformly bilayer and had some of the lowest Raman D/G ratios found in the literature. In addition, dry transfer experiments have been performed that have provided a direct measure of the adhesion energy, strength, and range of interactions at the sapphire/graphene interface. The adhesion energy of graphene to sapphire is lower than that of graphene grown on copper, but the strength of the graphene–sapphire interaction is higher. The quality of the several centimeter scale transfer was evaluated using Raman, SEM, and AFM as well as fracture mechanics concepts. Based on the evaluation of the electrical characteristics of the graphene synthesized in this work, this work has implications for several potential electronic applications. 

Abstract 2D memristors have demonstrated attractive resistive switching characteristics recently but also suffer from the reliability issue, which limits practical applications. Previous efforts on 2D memristors have primarily focused on exploring new material systems, while damage from the metallization step remains a practical concern for the reliability of 2D memristors. Here, the impact of metallization conditions and the thickness of MoS₂films on the reliability and other device metrics of MoS₂‐based memristors is carefully studied. The statistical electrical measurements show that the reliability can be improved to 92% for yield and improved by ≈16× for average DC cycling endurance in the devices by reducing the top electrode (TE) deposition rate and increasing the thickness of MoS₂films. Intriguing convergence of switching voltages and resistance ratio is revealed by the statistical analysis of experimental switching cycles. An “effective switching layer” model compatible with both monolayer and few‐layer MoS₂, is proposed to understand the reliability improvement related to the optimization of fabrication configuration and the convergence of switching metrics. The Monte Carlo simulations help illustrate the underlying physics of endurance failure associated with cluster formation and provide additional insight into endurance improvement with device fabrication optimization.